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Freescale Semiconductor /MK61F15WS /ENET /TGSR

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Interpret as TGSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)TF0 0 (0)TF1 0 (0)TF2 0 (0)TF3 0RESERVED

TF3=0, TF1=0, TF2=0, TF0=0

Description

Timer Global Status Register

Fields

TF0

Copy of Timer Flag for channel 0

0 (0): Timer Flag for Channel 0 is clear

1 (1): Timer Flag for Channel 0 is set
TF1

Copy of Timer Flag for channel 1

0 (0): Timer Flag for Channel 1 is clear

1 (1): Timer Flag for Channel 1 is set
TF2

Copy of Timer Flag for channel 2

0 (0): Timer Flag for Channel 2 is clear

1 (1): Timer Flag for Channel 2 is set
TF3

Copy of Timer Flag for channel 3

0 (0): Timer Flag for Channel 3 is clear

1 (1): Timer Flag for Channel 3 is set
RESERVED

no description available

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data